1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, particularly, to a semiconductor integrated circuit device having a main memory portion and a sub-memory portion formed in a semiconductor substrate and a data transfer circuit provided between the main memory portion and the sub-memory portion.
This application is based on Japanese Patent Application No. 11-62393, the contents of which are incorporated herein by reference.
2. Description of the Related Art
In general, a relatively low speed, inexpensive semiconductor device having the large memory capacity, such as general purpose DRAM, is used as the main memory in a computer system.
In recent computer systems, the operating speed of a DRAM constituting the main memory is increased along with the increase of the operating speed of the system, particularly, of the MPU. However, the operating speed of the DRAM is still insufficient and, in order to solve this problem, it is usual to provide a sub-memory between the MPU and the main memory. Such a sub-memory is generally called as a cache memory and is constructed with a high speed SRAM or an ECLRAM.
The cache memory is generally provided to the MPU externally or internally. Recently, a semiconductor device in which the DRAM constituting the main memory and the cache memory are mounted on the same semiconductor substrate has gained attention. Japanese Unexamined Patent Application, First publication Nos. Sho 57-20983, Sho 607690, Sho 62-38590 and Hei 1-146187 disclose examples of such semiconductor memory. Such semiconductor memory is sometimes called cache DRAM or CDRAM since it includes the DRAM and the cache memory. Data are bi-directionally transferred between the SRAM, which functions as the cache memory, and the DRAM which is the main memory.
These conventional arts have problems such as delays in data transfer operation in a case of cache mis-hit, and techniques which solve such problem has been proposed. Examples of the proposed techniques are disclosed in Japanese Unexamined Patent Applications, First Publication Nos. Hei 4-252486, Hei 4-318389 and Hei 5-2872. In the techniques, a latch or register function is provided in a bi-directional data transfer circuit between a DRAM portion and an SRAM portion, so that data transfer from the SRAM portion to the DRAM portion and data transfer from the DRAM portion to the SRAM portion can be done simultaneously, and the speed of data transfer (copy back) at the cache his-hit can be increased.
The above mentioned technique, however, has a limitation in the number of the circuits and in the number of the transfer bus lines because the bi-directional transfer gate circuit occupies a significant part of the area. Therefore, the number of bits which can be transferred between the DRAM array and the SRAM array at a time is limited to 16 bits. In general, as the number of bits transferred at a time decreases, the cache hit rate decreases.
Further, there is the recent problem of degradation of the cache hit rate when there are access requests from a plurality of processing devices as shown in FIG. 70. When the CDRAM or the EDRAM is used for the main memory as shown in FIG. 70 and there are access requests from a plurality of processing devices (memory masters), the cache hit rate is lowered and the speeding up of the whole system operation is restricted since the number of address requests for different sets (rows) may be increased. As the number of the systems having processing devices is increased, the memory portions must respond not only to one type of an access request but also various types of access requests.
In addition to the above-mentioned problem, this type of semiconductor memory receives an address signal synchronously with an external clock, and has the problem in that it takes time to generate an internal address signal.
FIG. 71 shows the construction of the circuit for generating the internal address signal within the conventional semiconductor memory. As shown in FIG. 71, a clock signal CLK, an external address signal Ai, various control signals CSB, RASB, CASB, and WEB are input through receiver circuits 6001 to 6006. The receiver circuits 6001 to 6006 convert these external signals into signals suitable for handling within the device. The clock signal CLK, which is input through the receiver circuit 6001, is input into an internal clock signal generating circuit 6010, which then generates an internal clock signal ICLK having a predetermined duty.
The address signal Ai, which is input through the receiver circuit 6002, is latched in an address latch circuit 6011, which then generates an internal address signal IAi. The various control signals CSB, RASB, CASB, and WEB are input into a command latch circuit 6012, which then generates a read/write command signal and an active command signal. A read/write signal generating circuit 6013 receives the read/write command signal, and generates a read/write signal and a column address latch signal. An active signal generating circuit 6014 receives the active command signal, and generates an active signal and a row address latch signal.
A column address latch circuit 6020 uses the column address latch signal from the read/write signal generating circuit as the trigger, latches the internal address signal LAi from the address latch circuit, and generates a column address signal Yi. This column address signal Yi is input into a counter circuit 6021, which then generates a counter output address signal. The counter output address signal is input into a column address latch circuit 6020 and is used, for example, as a column address signal in a burst mode. A row address latch circuit 6022 uses the row address latch signal from the active signal generating circuit 6014 as the trigger, latches the internal address signal IAi from the address latch circuit, and generates a row address signal Xi.
FIG. 72 shows the construction of the address latch circuit 6011.
As shown in FIG. 72, the address latch circuit 6011 comprises: a master latch circuit 6011A for allowing the address signal CAi, which is externally input, to pass when the internal clock signal is at a L (low) level, and latching the address signal CAi when the internal clock signal is at a H (high) level; and a slave latch circuit 6011B for allowing the signal from the master to pass when the internal clock signal is at the H level, and latching the signal when the internal clock signal is at the L level. That is, according to this construction, the address signal is latched by the master at the rising edge of the clock signal ICLK, and is latched by the slave at the falling edge of the clock signal ICLK, to thereby output the internal address signal IAi.
FIG. 73 shows the construction of the command latch circuit 6012.
As shown in FIG. 73, the various control signals CCS (control signals corresponding to CSB), CRAS (control signal corresponding to RASB), CCAS (control signal corresponding to CASB), and CWE (control signal corresponding to WEB), which are output from the above-mentioned receiver circuits 6003 to 6006, are latched in master latch circuits 6012A at the rising edge of the internal clock signal ICLK, and their logical product is calculated by a gate circuit 6012B. The signal, obtained from the logical product, is latched in a slave latch circuits 6012C at the falling edge of the internal clock signal ICLK, and the read/write command signal and the active command signal are generated.
FIG. 74 shows the construction of the read/write signal generating circuit.
The internal clock signal ICLK is delayed by a predetermined time by an inverter chain 6013A, and is input into one of the NAND circuits 6013B and 6013C. The above-described read/write command signal and the burst signal for activating the burst mode are input into the other NAND circuits 6013B or 6013C. Signals output from the NAND circuits 6013B and 6013C are input into the NAND circuit 6013D. A signal output from the NAND circuit 6013D is delayed by a predetermined time by an inverter chain 6013E, and becomes the read/write signal.
The internal clock ICLK delayed by the inverter chain 6013A and the read/write command signal is input into a NAND circuit 6013F, and an inverter 6013G outputs it as the column address latch signal. This column address latch signal is input as the trigger to the column address latch circuit 6020. The delay time of the column address latch signal is adjusted in the inverter chain 6013A so that the column address latch signal is activated after the address signal input into the column address latch circuit 6020 is set.
FIG. 75 shows the construction of the column address latch circuit 6020.
As shown in FIG. 75, the column address latch circuit 6020 comprises: a gate circuit 6020A for accepting the internal address signal IAi using the column address latch signal as the trigger; a gate circuit 6020B for accepting the counter output address signal using the counter output address latch signal as the trigger; a flip-flop 6020C for storing output from those gate circuits; and an inverter 6020D. When receiving a pulse signal at H level as the column address latch signal, the column address latch circuit 6020 receives the address signal LAi, stores it in the flip-flop 6020C, and outputs the address signal Yi.
Referring to the waveform chart of FIG. 76, the operation of the conventional internal address generating circuit system will be explained by way of an example of generating the column address signal Yi.
The internal clock generating circuit 6010 generates the internal clock signal ICLK from the external clock signal CLK. According to the internal clock signal ICLK, the address latch circuit 6011 latches the external address signal CAi, generates the internal address signal IAi, and outputs it to the column address latch circuit 6020.
On the other hand, according to the internal clock signal ICLK, the command latch circuit 6012 latches the various control signals CSB, RASB, CASB, and WEB, performs the predetermined logic operation, and outputs the read/write command signal. From the internal clock signal ICLK and the read/write signal, the read/write signal generating circuit 6013 generates the column address latch signal in which the pulse waveform of the internal clock signal ICLK is reflected. The column address latch circuit 6020 uses the column address latch signal as the trigger, latches the internal address signal IAi, and outputs the column address signal Yi.
With this construction of the internal address generating circuit system, the external address signal and the various control signals are latched in the address latch circuit 6011 and the command latch circuit 6012, and then the column address signal and the row address signal are generated according to the operation specified by the control signal. For example, in the process for generating the column address signal Yi, it takes time to generate the column address signal Yi because the external address signal passes through the address latch circuit 6011 which performs the master-slave latch operation according to the clock signal ICLK
Further, when the column address latch circuit 6020 latches the internal address signal IAi, the internal address signal IAi must be set. Therefore, the above-described inverter chain 6013A delays the column address latch signal, and, after the internal address signal IAi is set, the column address latch circuit 6020 starts its operation. Thus, the generation of the internal column address signal Yi is further delayed.